FAQ (Renesas)

use tab 3:Best Match Finder, to get best match
- input target baud rate
- input target error rate
- tool will try to find best match , base on freq :
  - 8MHz,16MHz,20MHz,24MHz,40MHz,80MHz,96MHz,120MHz

use tab 2:Manual Calculate, to calculate error rate
- input target Base Frequency
- input target LPRS/BRP0/NSPB
- input target baud rate

use tab 1:Auto Calculate, to calculate error rate
- input target Base Frequency
- input target baud rate
- input target display result

below is error rate result , when Base Frequency:40MHz

below is error rate result , when Base Frequency:24MHz

below is error rate result , when Base Frequency:16MHz

How to get RL78 slave PWM TDR/duty value

RL78 TDR formula

download(python)

use tab 1:manual input
- input pwm master TDR value (hex)
- input pwm slave TDR value (hex) , to calculate duty
- input pwm slave duty , to calculate slave TDR
- select check box , to enable auto calculate master TDR

use tab 2:calculate all TDR/duty value
- input pwm master TDR value (hex)

Notice about RH850/RL78 CAN module

* enable TDC when data phase with high baud rate

TDC_in_RL78

TDC_in_RH850

Nominal Bit Timing_in_RH850

NTSEG1[6:0] Bits : 4 to 128 Tq
NTSEG2[4:0] Bits : 2 Tq to 32 Tq
NSJW[4:0] Bits : 1 to 32 Tq

Data Bit Timing_in_RH850

DTSEG1[3:0] Bits : 2 to 16 Tq
DTSEG2[2:0] Bits : 2 to 8 Tq
DSJW[2:0] Bits Bits : 1 to 8 Tq

use tool to calcualte CAN FD timing
Bit-Rate-Calculation-Tool
use web site to calcualte CAN FD timing
bit-timing-calculator-can-fd
Timing_setting_in_RH850

* NBRP[9:0] = DBRP[7:0]
* when TDCE enable , NBRP[9:0] and DBRP[7:0] must equal vaule of 1 or less

Sample_Project_RH850_S1_CAN_FD_RX_Polling_No_Rule

Sample_Project_RH850_S1_CAN_FD_RX_Polling_No_Rule_5M

How_to_enable_TDC_in_RH850
- need to set TDCE and TDCOC
- need to set TDCO[6:0]
  - TDCO = SSP
- add below code in static void can_normal_mode_set(..)

    CAN_REG_SET(cst2[channel].CxFDCFG.UINT32,CAN_REG_BIT9,CAN_REG_LENGTH_1);    // TDCE = 1
    CAN_REG_SET(cst2[channel].CxFDCFG.UINT32,CAN_REG_BIT8,CAN_REG_LENGTH_1);    // TDCOC = 1
    //The SSP offset value = (set value of TDCO[6:0] bits + 1). 
    CAN_REG_SET(cst2[channel].CxFDCFG.UINT32,CAN_REG_BIT16,6);   // TDCO[6:0]

Below is PCAN tool setting to test 500K/5M

modify below code in const CAN_BUS_PARAMETER_T can_bus_parameter_ch1

    .NBRP                   = CAN_NBRP_1,
    .NTSEG1                 = CAN_NTSEG1_59TQ,
    .NTSEG2                 = CAN_NTSEG2_20TQ,
    .NSJW                   = CAN_NSJW_20TQ,

    .DBRP                   = CAN_DBRP_1,
    .DTSEG1                 = CAN_DTSEG1_5TQ,
    .DTSEG2                 = CAN_DTSEG2_2TQ,
    .DSJW                   = CAN_DSJW_2TQ,

    40MHz
    nominal : 500k
        sample rate : 75
        pre-scale : 1
        TSEG1 : 59
        TSEG2 : 20
        SJW : 20

    data : 5M
        sample rate : 75
        pre-scale : 1
        TSEG1 : 5
        TSEG2 : 2
        SJW : 5  
        
        SSP : 6

other Nominal Data Bit timing 1
- nominal : 500K , 75%
- data : 2M , 75%

    .NBRP                   = CAN_NBRP_1,
    .NTSEG1                 = CAN_NTSEG1_59TQ,
    .NTSEG2                 = CAN_NTSEG2_20TQ,
    .NSJW                   = CAN_NSJW_20TQ,

    .DBRP                   = CAN_DBRP_1,
    .DTSEG1                 = CAN_DTSEG1_14TQ,
    .DTSEG2                 = CAN_DTSEG2_5TQ,
    .DSJW                   = CAN_DSJW_5TQ,

    40MHz
    nominal : 500k
        sample rate : 75
        pre-scale : 1
        TSEG1 : 59
        TSEG2 : 20
        SJW : 20

    data : 2M
        sample rate : 75
        pre-scale : 1
        TSEG1 : 14
        TSEG2 : 5
        SJW : 5

other Nominal Data Bit timing 2
- nominal : 500K , 80%
- data : 2M , 70%

    .NBRP                   = CAN_NBRP_1,       //1U - 1U,
    .NTSEG1                 = CAN_NTSEG1_63TQ,  //63U - 1U,
    .NTSEG2                 = CAN_NTSEG2_16TQ,  //16U - 1U,
    .NSJW                   = CAN_NSJW_16TQ,    //16U - 1U,

    .DBRP                   = CAN_DBRP_1,       //1U - 1U,
    .DTSEG1                 = CAN_DTSEG1_13TQ,  //13U - 1U,
    .DTSEG2                 = CAN_DTSEG2_6TQ,   //6U - 1U,
    .DSJW                   = CAN_DSJW_6TQ,     //6U - 1U,

    40MHz
    nominal : 500k
        sample rate : 80
        pre-scale : 1
        TSEG1 : 63
        TSEG2 : 16
        SJW : 16

    data : 2M
        sample rate : 70
        pre-scale : 1
        TSEG1 : 13
        TSEG2 : 6
        SJW : 6

Sample_Project_RH850_S1_CAN_RX_Polling_No_Rule

How to set CAN frame or CAN FD frame
- modify CAN_FD_MODE_e mode to output classical CAN frame or CAN FD frame

typedef enum
{
    CAN_FD_MIX_MODE=0,
    CAN_FD_ONLY_MODE=1,
    CAN_STANDARD_MODE=2
}CAN_FD_MODE_e;

Some example code

RH850

single CH (CAN1)
Sample_Project_RH850_S1_CAN_FD_RX_Polling_No_Rule

Sample_Project_RH850_S1_CAN_FD_RX_Polling_With_Rule

Sample_Project_RH850_S1_CAN_FD_RX_Interrupt_No_Rule

Sample_Project_RH850_S1_CAN_FD_RX_Interrupt_With_Rule

single CH (CAN1 , high baud rate)
Sample_Project_RH850_S1_CAN_FD_RX_Polling_No_Rule_5M

single CH (CAN4)
Sample_Project_RH850_S1_CAN_FD_RX_No_Rule_CH4

single CH (CAN1 , CAN frame)
Sample_Project_RH850_S1_CAN_RX_Polling_No_Rule

multi CH (CAN1 , CAN4)
Sample_Project_RH850_S1_CAN_FD_MultiCH

RL78

RL78_F24_CAN_FD

RL78_F24_CAN

RL78_F13_CAN